1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device such as a dynamic random access memory (hereinafter referred to as DRAM) capable of stable operation.
2. Description of the Background Art
In recent years, demands for semiconductor devices have rapidly increased as information appliances remarkably come into wide use. From the functional point of view, devices with greater storage capacity and higher operation speed are in demand. Technological development of semiconductor devices having higher integration density, responsiveness and reliability is in progress to meet such demand.
A DRAM is a semiconductor memory device which permits random input/output of storage information. In general, the DRAM includes a memory cell array which is a storage region for storing a large amount of storage information, and peripheral circuitry necessary for inputting/outputting information to/from outside the device.
FIG. 34 is a block diagram showing the configuration of a general DRAM. Referring to FIG. 34, DRAM 50 includes a memory cell array 51 for storing data signals indicating storage information, a row and column address buffer 52 receiving an externally applied address signal used to select a memory cell which constitutes a unit storage circuit, a row decoder 53 and a column decoder 54 for decoding the address signal and designating the memory cell, a sense refresh amplifier 55 for amplifying a signal stored in the designated memory cell for reading, a data in buffer 56 and a data out buffer 57 for inputting/outputting data, and a clock generator 58 for generating a clock signal. Memory cell array 51 which occupies a large area on the semiconductor chip has a plurality of memory cells arranged in a matrix for storing unit storage information.
FIG. 35 is a diagram showing memory cells for 4 bits in the memory cell array. In FIG. 35, a memory cell includes a MOS (Metal Oxide Semiconductor) transistor, and a capacitor 16 having one electrode connected to MOS transistor 15, and is connected to a bit line 14 and a word line 17. Information is stored in capacitor 16 as charge. One memory cell shown is a so-called one-transistor-one-capacitor-type memory cell formed of one MOS transistor 15 and one capacitor 16 connected thereto. For its simple structure, this type of memory cell allows for improvement of the integration density of memory cell array, and is therefore in wide use in DRAMs which require large storage capacities.
In order to achieve greater storage capacities, the efforts to improve the integration density of a memory cell array has been made by changing the structures of elements such as a capacitor in a memory cell. The DRAM memory cells can be classified into several types depending on the structures of their capacitors. One type of memory cell, a stacked type memory cell will be detailed.
FIG. 36 is a plan view showing the structure of a conventional stacked type memory cell. FIG. 37 is a cross sectional view taken along line A--A in FIG. 36. Referring to FIGS. 36 and 37, the memory cell includes a p type region 151 in a semiconductor substrate 150, a gate insulating film 152, a field insulating film 153, a gate electrode 154 formed of part of a word line, a storage node 155 formed of polysilicon, a capacitor insulating film 156, a cell plate 157 formed of polysilicon, an interlayer insulating film 162, and a pair of n type source/drain regions 158a and 158b. One memory cell is formed of one MOS transistor and one capacitor isolated from each other by an interlayer insulating film. The MOS transistor includes n type source/drain region pair 158 and gate electrode 154. A capacitor 180 is formed of storage node 155 and cell plate 157 with capacitor insulating film 156 interposed therebetween. The storage node 155 of capacitor 180 is connected to the surface of n type source/drain region 158a of the MOS transistor through a columnar conductive layer 155a formed in interlayer insulating film 162.
Now, a method of forming such a stacked type memory cell will be described. Referring to FIG. 38, gate insulating film 152 and gate electrode 154 having a prescribed width are formed in a region isolated by a p type impurity region 166 and field insulating film 153 on semiconductor substrate 150 having p type region 151. The pair of n type source/drain regions 158a and 158b are then formed, for example, by means of ion implantation, thus completing the MOS transistor. Referring to FIG. 39, an interlayer insulating film 160 is formed on semiconductor substrate 150 so as to cover the MOS transistor. A contact hole 161 for a bit line is formed in interlayer insulating film 160 to expose a contact portion 201 including part of the surface of n type source/drain region 158b. Referring to FIG. 40, a bit line 159 to be connected to part of the surface of n type source/drain region 158b at contact portion 201 is formed. Referring to FIG. 41, interlayer insulating film 162 is then formed over bit line 159. A contact hole 163 for a storage node is formed in interlayer insulating film 162 to expose contact portion 200 including part of the surface of n type source/drain region 158a. Referring to FIG. 42, a columnar conductive layer 155a to be electrically connected to n type source/drain region 158a at contact portion 200 is formed in contact hole 163 for storage node. Storage node 155 to be electrically connected to columnar conductive layer 155a is formed. Referring to FIG. 43, cell plate 157 is formed on storage node 155 with capacitor insulating film 156 interposed therebetween. Interlayer insulating film 164, a metal interconnection 165 and other elements are formed on cell plate 157. A conventional stacked type memory cell is formed as described above.
In the above process of manufacturing, some patterns are not accurately photolithographed on the semiconductor substrate, resulting in pattern mismatch in the surface of the semiconductor substrate at a certain frequency. This is so-called misalignment, and this has been more often encountered as the device size has shrunk in recent years.
In the process of manufacturing, if a conventional stacked type memory cell has misalignment in a contact for storage node in particular, part of field insulating film 153 is sometimes removed as shown in FIG. 44. In such a case, part of columnar conductive layer 155a connected to storage node 155 of the capacitor comes into direct contact with p type region 151 at point A as shown in FIG. 44 without the interposition of n type source/region 158a.
In the vicinity of a junction between n type source/drain region 158a and p type region 151, electrons, i.e., carriers in the n type region, and holes, i.e., carriers in the p type region are recombined to form a depletion layer having a low carrier concentration, thereby electrically isolating conductive layer 155a and p type region 151. At point A without this depletion layer, however, columnar conductive layer 155a is electrically connected to the p type region 151 of the semiconductor substrate. The flow of charges stored at storage node 155 to p type region 151 through columnar conductive layer 155a, in other words junction leakage current increases, and the held data may be destroyed.
A p type impurity region 166 having an impurity concentration higher than the concentration of a p type impurity contained in the semiconductor substrate is formed under field insulating film 153 in order to enhance element isolation, and therefore, as columnar conductive layer 155a comes close to p type impurity region 166, the electric field tends to be intensified, further increasing the junction leakage current.
As stated above, the semiconductor devices with higher integration densities are in demand to cope with larger memory capacities required. In such an environment, for example in FIG. 37, the distance between columnar conductive layer 155a and gate electrode 154 or the distance between bit line 159 and gate electrode 154 is shrinking.
Thus, the electric field around the region under gate electrode 154 increases, and the MOS transistor may cause a short channel effect which sometimes impedes the semiconductor device from performing predetermined operations.
As described above, in a conventional stacked type memory cell structure, the problem associated with misalignment resulting from the shrinkage of device prevails, and particularly as for alignment in a contact for storage node, charges stored at the storage node flow to the semiconductor substrate, in other words junction leakage current increases, and held data is destroyed.
In association with increase in the integration density of semiconductor devices, the distance between a conductive layer having a capacitor connected therewith and a gate electrode shrinks, which intensifies the electric field around the region under the gate electrode, and the MOS transistor is sometimes encountered with a short channel effect. As a result, the semiconductor device sometimes does not perform semiconductor device sometimes does not perform predetermined operation.